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リコー電子デバイス株式会社

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0.5µm CMOS Analog Mixed Mode

Process Outline

  • 0.5µm P-Sub 1P3M (1-Poly and 3-Metal) Twin Well CMOS generic process.
  • Transistor Characterizations are as follows;
Device Tr.type Vth[V] *1 Ids[uA/um] Ioff[pA/um]
PMOS 6V Tr. -0.85 222 0.7
4V Tr. -0.85 120 0.15
Low Vth 3.3V -0.63 - 0.43
Std. CMOS 3.3V -0.73 112 0.13
5V I/O -0.80 120 < 1 (Max)
NMOS 6V Tr. 0.61 315 0.1
4V Tr. 0.63 358 0.2
Low Vth 3.3V 0.52 - 0.2
Std. CMOS 3.3V 0.79 327 0.08
5V I/O 0.95 372 < 1 (Max)
  • *1Extrapolated Threshold at Vd=0.1V
  • Vth tunable to match customer's needs.

Option Modules

  • Depletion Transistor.
  • Vertical PNP Transistor.
  • Triple well.
  • 2k-ohm/sq High Resistivity Poly Resister.(* Tunable high resistivity poly to match customer's needs.)
  • Low temperature coefficient Poly Resistor.
  • Double Poly Capacitor (PiP).
  • Laser Trimming Fuse.

Design Environment

  • BSIM3V3 based on analog oriented extraction is used for SPICE simulation.
  • SPICE parameters are ready for HSPICE, SPECTRE and Smart SPICE.
  • Characterization report is available.
  • Logic libraries and I/O libraries are available.
  • ESD protection circuit is available.