The VDD pin on voltage detectors in general also acts as the voltage detection pin (SENSE pin). if the input voltage to the VDD pin becomes lower than the minimum operating voltage, the voltage detector becomes unstable operation and is unable to maintain the reset signal level. As shown in the following figures, reset signal (VOUT) becomes unstable on CMOS output products and reset signal (VOUT) is equalized to the pull-up voltage in the Nch. open drain output products.
Since the voltage detector with SENSE pin type separates the SENSE pin from the VDD pin, the reset signal can be maintained as long as voltage is supplied to the VDD pin even when the input voltage to the SENSE pin becomes lower then the minimum operating voltage.
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